1. Field of the Invention
The present invention relates to a frequency corrector which is mounted in a large-scale integration (LSI) circuit having a clock function, and more particularly to a frequency corrector for correcting a clock signal having a frequency of, e.g. 32.768 kHz, or the like output from a crystal-oscillator or the like, and to a clocking apparatus using the same.
2. Description of the Background Art
Conventionally, a technology relating to a clocking apparatus having a frequency corrector has been disclosed by U.S. Pat. No. 5,481,507 to Suzuki et al. The electronic clocking apparatus, device and method for determining a correction value disclosed by Suzuki et al., corrects a deviation in oscillating frequency generated by a clock oscillator, thereby removing trimming capacitor for adjusting oscillating frequency.
As seen from Suzuki et al., as a frequency corrector that corrects a clock signal having a frequency of 32.768 kHz output from a crystal-oscillator in the order of ppm (=1/1,000,000), the type of correcting a clock signal by means of a trimming capacitor mounted outside an LSI device has conventionally been predominant. However, recently, a nonvolatile type of memory or the like is mounted in an LSI device in many cases, so that a solution is growing popular in which a frequency corrector is mounted in a counter in an LSI device to correct a frequency of 1 or 2 Hz signal, corresponding to a period of 1 or 0.5 second, respectively, used in a clocking apparatus.
As a frequency corrector has been known which corrects a frequency by means of a counter such as R2051 which is a real-time clock (RTC) manufactured by Ricoh Company, Ltd., www.ricoh.com/LSI/product_rtc/2wire/r2051k/index.html. The frequency corrector is, as described in Suzuki et al., as well, composed of a correction value memory that stores correction values, and a variable frequency divider circuit which is capable of changing a frequency dividing ratio on the basis of the correction values and divides a clock signal having a frequency of 32.768 kHz to output a 1 or 2 Hz signal. Thus, the frequency corrector is configured to change the number of clock pulses of the variable frequency divider circuit on the basis of the correction values stored in the correction value memory so as to adjust a progress or delay of the clock, thereby correcting it to an accuracy of 1.5 ppm or 0.5 ppm, corresponding to the interval of once per 20 or 60 seconds, respectively.
However, the conventional frequency corrector suffers from the following problems. First, the variable frequency divider circuit in the conventional clocking apparatus, as exemplified as shown in FIG. 15, has a second counter adapted to count a 1-Hz signal, corresponding to a period of one second, output from the variable frequency divider circuit, and count up from “00” to “59” seconds, repeating the counting up from 00 to 59 seconds. Then, a frequency correction once per 60 seconds is performed during the second counter indicating 59 seconds to reset the variable frequency divider circuit. Not only the signals at the respective frequencies of 4.096 kHz to 1.024 kHz but also the signals at other frequencies are reset once per 60 seconds.
In a method for correcting frequencies at an interval of 20 or 60 seconds as done by the conventional frequency corrector, in a case in which a correction value is larger, for example, the clock time is made progress by +100 ppm with an accuracy of 0.5 ppm, the final one of the 60 seconds, i.e. the time that the second counter indicates 59 seconds, is shortened by a period corresponding to 200 clock pulses (about 6.1 ms) of a clock signal having a frequency of 32.768 kH. In this case, a signal at 1.024 kHz, for example, falling in the range of 32.768 kHz to 1 Hz (1 second) provided by the variable frequency divider circuit has a cycle of 1,017.75 pulses. As a result, the frequency is not corrected between the first cycle and the 1,017th cycle of the signal at 1.024 kHz, which leads to a correction timing once per 60 seconds causing the signal at 1.024 kHz having its cycle shorter, which is a 0.75 cycle. Therefore, in a case in which the signal at 1.024 kHz is used as a drive clock signal for a timer for stopwatch serving as a peripheral circuit of an LSI for example, it is impossible to perform accurate clocking by that stopwatch.
Secondly, the frequency corrector as disclosed by Suzuki et al., has a circuit generating correction values which is complicated. Moreover, because the crystal oscillating frequency of 32.768 kHz is divided down to 1 Hz by the variable frequency divider circuit, the variable frequency divider circuit is made complicated in circuit configuration. Therefore, the circuit scale of the entire frequency corrector is larger, and the power consumption is increased accordingly. Thus, when such a frequency corrector is incorporated into portable equipment or the like, the power consumption of its battery is increased so as to quickly die, which puts a limit on its use or the like.